Figure 12. Scaling of costs in Figure 10 for larger systems using an all erasure architecture, a no erasure architecture, or a hybrid erasure architecture. All hybrid points sweep over and select the best erasure fraction. Shaded region represents area of possible hybrid erasure values in between analytical upper bound and approximate observed circuit-level lower bound. Top: Minimum possible logical error rate for fixed transmon cost. Background gradient indicates resulting single chip yield for a defect rate of \(10^{-3}\). Bottom: Minimum possible number of transmons for a target logical error rate.