Figure 9. Projecting logical performance to higher code distances under fixed $(p_\text{g}, p_\text{sh}) = (10^{-3}, 10^{-5})$ for various $p_\text{id}$ with SNAQ $\rho=2$. (a) SNAQ and Bilinear give diminishing returns as code distance increases due to an increase in shuttling and idling errors with larger codeblock size, while UnitCell exhibits consistent error suppression as distance is increased. (b) Logical error rate as a function of readout count, which may be an important driver of packaging cost, showing that SNAQ outperforms Bilinear and is competitive with UnitCell. (c) Logical error rate as a function of total component area per logical qubit. For sufficiently-low $p_\text{id}$, SNAQ achieves better logical performance at significantly reduced total chip area compared to both baselines.